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COP840CJ COP842CJ COP940CJ COP942CJ 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector
August 1996
COP840CJ COP842CJ COP940CJ COP942CJ 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector
General Description
The COP840CJ is a member of the COP8TM feature family 8-bit microcontroller It is a fully static Microcontroller fabricated using double-metal silicon gate microCMOS technology This low cost microcontroller is a complete microcomputer containing all system timing interrupt logic ROM RAM and I O necessary to implement dedicated control functions in a variety of applications Features include an 8-bit memory mapped architecture MICROWIRETM serial I O a 16-bit timer counter with capture register a multisourced interrupt Comparator WATCHDOGTM Timer Modulator Timer Brown out detection and Multi Input Wake-up Each I O pin has software selectable options to adapt the device to the specific application The device operates over a voltage range of 2 5V-6 0V High throughput is achieved with an efficient regular instruction set operating at a 1 ms per instruction rate Low radiated emissions are achieved by gradual turn on output drivers and internal ICC filters on the chip logic and crystal oscillator
I O Features
Y Y
Y Y Y Y
Memory mapped I O Software selectable I O options (TRI-STATE push-pull weak pull-up input high impedance input) High current outputs (8 pins) Schmitt trigger inputs on Port G MICROWIRE PLUSTM serial I O Packages 20 DIP SO with 16 I O pins 28 DIP SO with 24 I O pins
CPU Instruction Set Features
Y Y
Y Y Y
Key Features
Y Y Y Y
1 ms instruction cycle time Three multi-source interrupts servicing External interrupt with selectable edge Timer interrupt Software interrupt Versatile and easy to use instruction set 8-bit Stack Pointer (SP) stack in RAM Two 8-bit register indirect data memory pointers (B and X)
Y
Y Y Y Y
Multi-Input wake-up (on the 8-bit Port L) Brown out detection Analog comparator Modulator Timer (high speed PWM timer for IR transmission) 16-bit multi-function timer supporting PWM mode External event counter mode Input capture mode Quiet design (low radiated emissions) Integrated capacitor for the R C oscillator 2048 bytes of ROM 128 bytes of RAM
Fully Static CMOS
Y Y Y
Low current drain (typically k 1 mA) Single supply operation 2 5V to 6 0V Temperature ranges 0 C to a 70 C b40 C to a 85 C b 55 C to a 125 C
Development Support
Y Y
Emulation and OTP devices Real time emulation and full program debug offered by MetaLink's development system
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation WATCHDOGTM MICROWIRE PLUSTM COP8TM and MICROWIRETM are trademarks of National Semiconductor Corporation iceMASTERTM is a trademark of MetaLink Corporation C1996 National Semiconductor Corporation TL DD12851 RRD-B30M96 Printed in U S A
TL DD 12851 - 1
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Connection Diagrams
Pin Assignment
Port PIN L0 L1 L2 L3 L4 L5 L6 L7 G0 G1 G2 G3 G4 G5 G6 G7 I0 I1 I2 I3 D0 D1 D2 D3 VCC GND CKI RESET Type IO IO IO I I I I I I I I I I I O O O O O O O O O O O I I I I I I O O O O 6 15 5 16 ALT Funct MIWU CMPOUT MIWU CMPINb MIWU CMPIN a MIWU MIWU MIWU MIWU MIWU MODOUT INTR 20-Pin 7 8 9 10 11 12 13 14 17 18 19 20 1 2 3 4 28-Pin 11 12 13 14 15 16 17 18 25 26 27 28 1 2 3 4 7 8 9 10 19 20 21 22 6 23 5 24
TL DD 12851-2
Top View Order Number COP840CJ-XXX N or COP840CJ-XXX M COP940CJ-XXX N or COP940CJ-XXX M See NS Package Number N28B or M28B
TIO SO SK SI CKO
TL DD 12851-3
Top View Order Number COP842CJ-XXX N or COP842CJ-XXX M COP942CJ-XXX N or COP942CJ-XXX M See NS Package Number N20A or M20B FIGURE 1 Connection Diagrams
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Absolute Maximum Ratings
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (source) 7 0V b 0 3V to VCC a 0 3V 80 mA Total Current out of GND Pin (sink) Storage Temperature Range 80 mA
b 65 C to a 150 C
Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings
DC Electrical Characteristics COP94x 0 C s TA s a 70 C unless otherwise specified
Parameter Operating Voltage COP94xCJ COP94xCJH Power Supply Ripple (Note 1) Supply Current (Notes 2 5) CKI e 10 MHz R e 2 2k CKI e 4 MHz R e 4 7k CKI e 4 MHz R e 4 7k CKI e 1 MHz R e 20k HALT Current with Brown Out Disabled (Note 3) HALT Current with Brown Out Enabled Brown Out Trip Level (Brown Out Enabled) INPUT LEVELS (VIH VIL) Reset CKI Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current L- and G-Port Hysteresis Output Current Levels D Outputs Source Sink L4 - L7 Output Sink All others Source (Weak Pull-up Mode) Sink (Push-Pull Mode) TRI-STATE Leakage VCC e 6 0V VCC e 6 0V Condition Brown Out Disabled Peak-to-Peak VCC VCC VCC VCC VCC
e e e e e
Min 25 45
Typ
Max 45 60 0 1 VCC 80 60 25 15 8 100
Units V V V mA mA mA mA mA mA
6V tC e 1 ms 6V tC e 2 5 ms 4 5V tC e 2 5 ms 4 5V tC e 10 ms 6V CKI e 0 MHz
k22 k 50
VCC e 6V CKI e 0 MHz
19
31
39
V
0 8 VCC 0 2 VCC 0 7 VCC 0 2 VCC
b2 b 40 a2 b 250
V V V V mA mA V
0 05 VCC
0 35 VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC
e e e e e e e e e
4 5V 2 5V 4 5V 2 5V 4 5V 4 5V 2 5V 4 5V 2 5V
VOH e 3 8V VOH e 1 8V VOL e 1 0V VOH e 0 4V VOL e 2 5V VOH e 3 2V VOH e 1 8V VOL e 0 4V VOL e 0 4V
b0 4 b0 2
10 2 15
b 10 b2 5 b 110 b 33
mA mA mA mA mA mA mA mA mA mA
16 07 b2 0
a2 0
3
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DC Electrical Characteristics COP94x 0 C s TA s a 70 C unless otherwise specified (Continued)
Parameter Allowable Sink Source Current per Pin D Outputs L4 - L7 (sink) All Others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage Vr Input Capacitance Load Capacitance on D2
Note 1 Rate of voltage change must be k 10V ms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and crystal configurations HALT test conditions L and G0 G5 ports configured as outputs and set high The D port set to zero All inputs tied to VCC The comparator and the Brown Out circuits are disabled Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to k 14V Note 5 The Resistor values are for R C only
Condition
Min
Typ
Max 15 20 3
g100
Units mA mA mA mA V
500 ns Rise and Fall Time (min)
20 7 1000
pF pF
AC Electrical Characteristics COP94x 0 C s TA s a 70 C unless otherwise specified
Parameter Instruction Cycle Time (tC) Crystal Resonator R C Oscillator VCC Rise Time when Using Brown Out Frequency at Brown Out Reset CKI Frequency for Modulator Output CKI Clock Duty Cycle (Note 1) Rise Time (Note 1) Fall Time (Note 1) Inputs tSetup tHold Output Propagation Delay tPD1 tPD0 SO SK All Others Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time MICROWIRE Setup Time (tmWS) MICROWIRE Hold Time (tmWH) MICROWIRE Output Propagation Delay (tmPD) Reset Pulse Width
Note 1 Parameter sampled but not 100% tested
Condition 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V
Min 1 25 2 5 50
Typ
Max DC DC DC DC 4 4
Units ms ms ms ms ms MHz MHz % ns ns ns ns ns ns
fr e Max fr e 10 MHz ext clock fr e 10 MHz ext clock 4 5V s VCC k 6 0 2 5V s VCC k 4 5 4 5V s VCC k 6 0 2 5V s VCC k 4 5 RL e 2 2k CL e 100 pF 4 5V s VCC k 6 0 2 5V s VCC k 4 5 4 5V s VCC k 6 0 2 5V s VCC k 4 5
40
60 12 8
200 500 60 150
07 1 75 1 5 1 1 1 1 1 20 56 220 10
ms ms ms ms tC tC tC tC tC ns ns ns ms
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Absolute Maximum Ratings
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at any Pin Total current into VCC pin (source) 7 0V b 0 3V to VCC a 0 3V 80 mA Total current out of GND pin (sink) Storage Temperature Range 80 mA
b 65 C to a 150 C
Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings
DC Electrical Characteristics COP84x b40 C s TA s a 85 C unless otherwise specified
Parameter Operating Voltage Power Supply Ripple (Note 1) Supply Current (Notes 2 5) CKI e 10 MHz R e 2 2k CKI e 4 MHz R e 4 7k CKI e 4 MHz R e 4 7k CKI e 1 MHz R e 20k HALT Current with Brown Out Disabled (Note 3) HALT Current with Brown Out Enabled Brown Out Trip Level (Brown Out Enabled) INPUT LEVELS (VIH VIL) Reset CKI Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current L- and G-Port Hysteresis Output Current Levels D Outputs Source Sink L4 - L7 Output Sink All Others Source (Weak Pull-Up Mode) Sink (Push-Pull Mode) TRI-STATE Leakage VCC e 6 0V VCC e 6 0V Condition Brown Out disabled Peak-to-Peak VCC VCC VCC VCC VCC
e e e e e
Min 25
Typ
Max 60 0 1 VCC 80 60 25 15
Units V V mA mA mA mA mA mA
6V tC e 1 ms 6V tC e 2 5 ms 4 5V tC e 2 5 ms 4 5V tC e 10 ms 6V CKI e 0 MHz
k25 k 50
10 100
VCC e 6V CKI e 0 MHz
18
31
42
V
0 8 VCC 0 2 VCC 0 7 VCC 0 2 VCC
b2 b 40 a2 b 250
V V V V mA mA V
0 05 VCC
0 35 VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC
e e e e e e e e e
4 5V 2 5V 4 5V 2 5V 4 5V 4 5V 2 5V 4 5V 2 5V
VOH e 3 8V VOH e 1 8V VOL e 1 0V VOH e 0 4V VOL e 2 5V VOH e 3 2V VOH e 1 8V VOL e 0 4V VOL e 0 4V
b0 4 b0 2
10 2 15
b 10 b2 5 b 110 b 33
mA mA mA mA mA mA mA mA mA mA
16 07 b2 0
a2 0
5
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DC Electrical Characteristics COP84x b40 C s TA s a 85 C unless otherwise specified (Continued)
Parameter Allowable Sink Source Current per Pin D Outputs L4 - L7 (sink) All Others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage Vr Input Capacitance Load Capacitance on D2
Note 1 Rate of voltage change must be k 10V ms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and crystal configurations HALT test conditions L and G0 G5 ports configured as outputs and set high The D port set to zero All inputs tied to VCC The comparator and the Brown Out circuits are disabled Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to k 14V Note 5 The Resistor values are for R C only
Condition
Min
Typ
Max 15 20 3
g100
Units mA mA mA mA
500 ns Rise and Fall Time (min)
20 7 1000
V pF pF
AC Electrical Characteristics COP84x b40 C s TA s a 85 C unless otherwise specified
Parameter Instruction Cycle Time (tC) Crystal Resonator R C Oscillator VCC Rise Time when Using Brown Out Frequency at Brown Out Reset CKI Frequency for Modulator Output CKI Clock Duty Cycle (Note 1) Rise Time (Note 1) Fall Time (Note 1) Inputs tSetup tHold Output Propagation Delay tPD1 tPD0 SO SK All Others Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer input low time MICROWIRE Setup Time (tmWS) MICROWIRE Hold Time (tmWH) MICROWIRE Output Propagation Delay (tmPD) Reset Pulse Width
Note 1 Parameter sampled but not 100% tested
Condition 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V 4 5V k VCC k 6 0V 2 5V s VCC k 4 5V
Min 1 25 2 5 50
Typ
Max DC DC DC DC 4 4
Units ms ms ms ms ms MHz MHz % ns ns ns ns ns ns
fr e Max fr e 10 MHz ext clock fr e 10 MHz ext clock 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V RL e 2 2k CL e 100 pF 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V 4 5V s VCC k 6 0V 2 5V s VCC k 4 5V
40
60 12 8
200 500 60 150
07 1 75 1 5 1 1 1 1 1 20 56 220 10
ms ms ms ms tC tC tC tC tC ns ns ns ms
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AC Electrical Characteristics COP84X (Continued)
TL DD 12851 - 4
FIGURE 1 MICROWIRE PLUS Timing
Typical Performance Characteristics (b40 C s TA s a 85 C)
Port D Sink Current
Halt Current with Brown Out Disabled
TL DD 12851 - 5
TL DD 12851 - 6
Halt Current with Brown Out Enabled
Halt Current with Comparator Enabled
TL DD 12851 - 7
TL DD 12851 - 8
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Typical Performance Characteristics (b40 C s TA s a 85 C) (Continued)
Ports L G Push-Pull Source Current
Ports L G Push-Pull Sink Current
TL DD 12851-9
TL DD 12851 - 10
Port D Source Current
Port D Sink Current
TL DD 12851-11
TL DD 12851 - 12
Brown Out Voltage vs Temperature
TL DD 12851 - 13
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Pin Descriptions
VCC and GND are the power supply pins CKI is the clock input This can come from an external source a R C generated oscillator or a crystal (in conjunction with CKO) See Oscillator description RESET is the master reset input See Reset description PORT I is a 4-bit Hi-Z input port PORT L is an 8-bit I O port There are two registers associated with the L port a data register and a configuration register Therefore each L I O bit can be individually configured under software control as shown below Port L Config 0 0 1 1 PORT L Data 0 1 0 1 Port L Setup Hi-Z input (TRI-STATE) Input with weak pull-up Push-pull zero output Push-pull one output Three data memory address locations are allocated for this port one for data register 00D4 one for configuration register 00D5 and one for the input pins 00D6 Since G6 and G7 are Hi-Z input only pins any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded Reading the G6 and G7 configuration bits will return zeros Note that the device will be placed in the Halt mode by writing a ``1'' to the G7 data bit Six pins of Port G have alternate features G0 INTR (an external interrupt) G3 TIO (timer counter input output) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock I O) G6 SI (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart input general purpose input (if clock option is R C- or external clock) Pins G1 and G2 currently do not have any alternate functions The selection of alternate Port G functions is done through registers PSW 00EF to enable external interrupt and CNTRL1 00EE to select TIO and MICROWIRE operations PORT D is a four bit output port that is preset high when RESET goes low One data memory address location is allocated for the data register 00DC
Note Care must be exercised with the D2 pin operation At RESET the external loads on this pin must ensure that the output voltages stay above 0 8 VCC to prevent the chip from entering special modes Also keep the external loading on D2 to k 1000 pF
Three data memory address locations are allocated for this port one each for data register 00D0 configuration register 00D1 and the input pins 00D2 Port L has the following alternate features L0 MIWU or CMPOUT L1 MIWU or CMPINb L2 MIWU or CMPIN a L3 MIWU L4 MIWU (high sink current capability) L5 MIWU (high sink current capability) L6 MIWU (high sink current capability) L7 MIWU or MODOUT (high sink current capability) The selection of alternate Port L functions is done through registers WKEN 00C9 to enable MIWU and CNTRL2 00CC to enable comparator and modulator All eight L-pins have Schmitt Triggers on their inputs PORT G is an 8-bit port with 6 I O pins (G0-G5) and 2 input pins (G6 G7) All eight G-pins have Schmitt Triggers on the inputs There are two registers associated with the G port a data register and a configuration register Therefore each G port bit can be individually configured under software control as shown below Port G Config 0 0 1 1 Port G Data 0 1 0 1 PORT G Setup Hi-Z input (TRI-STATE) Input with weak pull-up Push-pull zero output Push-pull one output
Functional Description
The internal architecture is shown in the block diagram Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device ALU AND CPU REGISTERS The ALU can do an 8-bit addition subtraction logical or shift operations in one cycle time There are five CPU registers A is the 8-bit Accumulator register PC is the 15-bit Program Counter register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is the 8-bit address register and can be auto incremented or decremented X is the 8-bit alternate address register and can be auto incremented or decremented SP is the 8-bit stack pointer which points to the subroutine stack (in RAM) B X and SP registers are mapped into the on-chip RAM The B and X registers are used to address the on-chip RAM The SP register is used to address the stack in RAM during subroutine calls and returns The SP must be initialized by software before any subroutine call or interrupts occur
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Functional Description (Continued)
MEMORY The memory is separated into two memory spaces program and data PROGRAM MEMORY Program memory consists of 2048 x 8 ROM These bytes of ROM may hold instructions or constant data The memory is addressed by the 15-bit program counter (PC) ROM can be indirectly read by the LAID instruction for table lookup
TL DD 12851 - 14
DATA MEMORY The data memory address space includes on-chip RAM I O and registers Data memory is addressed directly by instructions or indirectly through the B X and SP registers The device has 128 bytes of RAM Sixteen bytes of RAM are mapped as ``registers'' these can be loaded immediately decremented and tested Three specific registers X B and SP are mapped into this space the other registers are available for general usage The instruction set permits any bit in memory to be directly set reset or tested All I O and registers (except A and PC) are memory mapped therefore I O bits and register bits can be directly and individually set reset and tested except the write once only bit (WDREN WATCHDOG Reset Enable) and the unused and read only bits in the CNTRL2 and WDREG registers
Note RAM contents are undefined upon power-up
RC l 5 x Power Supply Rise Time
FIGURE 2 Recommended Reset Circuit The device comes out of the HALT mode when the RESET pin is pulled low In this case the user has to ensure that the RESET signal is low long enough to allow the oscillator to restart An internal 256 tC delay is normally used in conjunction with the two pin crystal oscillator When the device comes out of the HALT mode through Multi-Input Wake-up this delay allows the oscillator to stabilize The following additional actions occur after the device comes out of the HALT mode via the RESET pin If a two pin crystal resonator oscillator is being used RAM Contents Timer T1 and A Contents WATCHDOG Timer Prescaler Counter UNAFFECTED UNKNOWN CHANGED
Reset
EXTERNAL RESET The RESET input pin when pulled low initializes the microcontroller The user must insure that the RESET pin is held low until VCC is within the specified voltage range and the clock is stabilized An R C circuit with a delay 5x greater than the power supply rise time is recommended (Figure 2) The device immediately goes into reset state when the RESET input goes low When the RESET pin goes high the device comes out of reset state synchronously The device will be running within two instruction cycles of the RESET pin going high The following actions occur upon reset Register Port L Port G Port D PC RAM Contents Initialization TRI-STATE TRI-STATE HIGH CLEARED RANDOM with Power On Reset UNAFFECTED with external Reset (power already applied) Same as RAM
If the external or RC clock option is being used RAM Contents Timer T1 and A Contents WATCHDOG Timer Prescaler Counter UNCHANGED UNCHANGED CHANGED
The external RESET takes priority over the Brown Out Reset
Note If the RESET pin is pulled low while Brown Out occurs (Brown Out circuit has detected Brown Out condition) the external reset will not occur until the Brown Out condition is removed External reset has priority only if VCC is greater than the Brown Out Voltage
B X SP
PSW CNTRL1 CNTRL2 CLEARED and WDREG Reg Multi-Input Wake-up Reg (WKEDG WKEN) CLEARED (WKPND) UNKNOWN Data and Configuration Registers for L and G WATCHDOG Timer CLEARED Prescaler Counter each loaded with FF
WATCHDOG RESET With WATCHDOG enabled the WATCHDOG logic resets the device if the user program does not service the WATCHDOG timer within the selected service window The WATCHDOG reset does not disable the WATCHDOG Upon WATCHDOG reset the WATCHDOG Prescaler Counter are each initialized with FF Hex The following actions occur upon WATCHDOG reset that are different from external reset WDREN WATCHDOG Reset Enable bit UNCHANGED WDUDF WATCHDOG Underflow bit UNCHANGED
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Reset (Continued)
Additional initialization actions that occur as a result of WATCHDOG reset are as follows Port L Port G Port D PC RAM Contents B X SP PSW CNTRL1 and CNTRL2 (except WDUDF Bit) Registers Multi-Input Wake-up Registers (WKEDG WKEN) (WKPND) Data and Configuration Registers for L and G WATCHDOG Timer TRI-STATE TRI-STATE HIGH CLEARED RANDOM UNAFFECTED CLEARED The following actions occur as a result of Brown Out reset Port L Port G Port D PC RAM Contents B X SP PSW CNTRL1 CNTRL2 and WDREG Registers Multi-Input Wake-up Registers (WKEDG WKEN) CLEARED UNKNOWN CLEARED Prescaler Counter each loaded with FF (WKPND) Data and Configuration Registers for L and G WATCHDOG Timer Timer T1 and Accumulator BROWN OUT RESET The on-board Brown Out detection circuit resets the device when the operating voltage (VCC) is lower than the Brown Out voltage The device is held in reset when VCC stays below the Brown Out voltage The device will remain in RESET as long as VCC is below the Brown Out Voltage The device will resume execution if VCC rises above the Brown Out Voltage If a two pin crystal resonator clock option is selected the Brown Out reset will trigger a 256 tc delay This delay allows the oscillator to stabilize before the device exits the reset state The delay is not used if the clock option is either R C or external clock The contents of data registers and RAM are unknown following a Brown Out reset The external reset takes priority over Brown Out Reset and will deactivate the 256 tc cycles delay if in progress The Brown Out reset takes priority over the WATCHDOG reset TRI-STATE TRI-STATE HIGH CLEARED RANDOM UNKNOWN CLEARED CLEARED UNKNOWN CLEARED Prescaler Counter each loaded with FF Unknown data after coming out of the HALT (through Brown Out Reset) with any Clock option
Note The Development system will detect the BROWN OUT RESET externally and will force the RESET pin low The Development System does not emulate the 256 tc delay
Brown Out Detection
An on-board detection circuit monitors the operating voltage (VCC) and compares it with the minimum operating voltage specified The Brown Out circuit is designed to reset the device if the operating voltage is below the Brown Out voltage (between 1 8V - 4 2V at b40C to a 85C) The Minimum operating voltage for the device is 2 5V with Brown Out disabled but with Brown Out enabled the device is guaranteed to operate properly down to minimum Brown Out voltage (Max frequency 4 MHz) For temperature range of 0 C - 70 C the Brown Out voltage is expected to be between 1 9V and 3 9V The circuit can be enabled or disabled by Brown Out mask option If the device is intended to operate at lower VCC (lower than Brown Out voltage VBO max) the Brown Out circuit should be disabled by the mask option The Brown Out circuit may be used as a power-up reset provided the power supply rise time is slower than 50 ms (0V - 6 0V) Brown Out should not be used in frequencies over 4 MHz
Note Brown Out Circuit is active in HALT mode (with the Brown Out mask option selected)
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Oscillator Circuits
EXTERNAL OSCILLATOR By selecting the external oscillator option the CKI pin can be driven by an external clock signal provided it meets the specified duty cycle rise and fall times and input levels The G7 CKO is available as a general purpose input G7 and or Halt control CRYSTAL OSCILLATOR By selecting the crystal oscillator option the G7 CKO pin is connected as a clock output CKI and G7 CKO can be connected to make a crystal controlled oscillator Table I shows the clock frequency for different component values See Figure 3 for the connections R C OSCILLATOR By selecting the R C oscillator option connecting a resistor from the CKI pin to VCC makes a R C oscillator The capacitor is on-chip The G7 CKO pin is available as a general purpose input G7 and or Halt control Adding an external capacitor will jeopardize the clock frequency tolerance and increase EMI emissions Table II shows the clock frequency for the different resistor values The capacitor is on-chip See Figure 3 for the connections
TL DD 12851 - 15
FIGURE 3 Clock Oscillator Configurations TABLE I Crystal Oscillator Configuration (TA e 25 C) R1 (kX) 0 0 56 R2 (MX) 1 1 1 C1 (pF) 30 30 200 C2 (pF) 30 - 36 30 - 36 100 - 156 CKI Freq (MHz) 10 4 0 455 Conditions VCC e 5V VCC e 5V VCC e 5V
TABLE II R C Oscillator Configuration (Part- To- Part Variation) R (kX) (Note 1) 22 47 20 0 CKI Freq (MHz) 7 0 g15% 4 2 g10% 1 1 g10% Temp
b 40 C b a 85 C b 40 C b a 85 C b 40 C b a 85 C
VCC 4 5V - 5 5V 4 5V - 5 5V 4 5V - 5 5V
Note 1 The resistance level is calculated with a total of 5 3 pF capacitance added from the printed circuit board It is important to take this into account when figuring the clock frequency
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Oscillator Circuits (Continued)
HALT Mode The device is a fully static device The device enters the HALT mode by writing a one to the G7 bit of the G data register Once in the HALT mode the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted In this mode the chip will only draw leakage current (output current and DC current due to the Brown Out circuit if Brown Out is enabled) The device supports four different methods of exiting the HALT mode The first method is with a low to high transition on the CKO (G7) pin This method precludes the use of the crystal clock configuration (since CKO is a dedicated output) It may be used either with an RC clock configuration or an external clock configuration The second method of exiting the HALT mode is with the Multi-Input Wake-up feature on the L port The third method of exiting the HALT mode is by pulling the RESET input low The fourth method is with the operating voltage going below Brown Out voltage (if Brown Out is enabled by mask option) If the two pin crystal resonator oscillator is being used and Multi-Input Wake-up or Brown Out causes the device to exit the HALT mode the WAKE-UP signal does not allow the chip to start running immediately since crystal oscillators have a delayed start up time to reach full amplitude and frequency stability The WATCHDOG timer (consisting of an 8-bit prescaler followed by an 8-bit counter) is used to generate a fixed delay of 256 tC to ensure that the oscillator has indeed stabilized before allowing instruction execution In this case upon detecting a valid WAKE-UP signal only the oscillator circuitry is enabled The WATCHDOG Counter and Prescaler are each loaded with a value of FF Hex The WATCHDOG prescaler is clocked with the tC instruction cycle (The tC clock is derived by dividing the oscillator clock down by a factor of 10) The schmitt trigger following the CKI inverter on the chip ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs This Schmitt trigger is not part of the oscillator closed loop The start-up time-out from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip The delay is not activated when the device comes out of HALT mode through RESET pin Also if the clock option is either RC or External clock the delay is not used but the WATCHDOG Prescaler Counter contents are changed The Development System will not emulate the 256 tC delay The RESET pin or Brown Out will cause the device to reset and start executing from address X'0000 A low to high transition on the G7 pin (if single pin oscillator is used) or MultiInput Wake-up will cause the device to start executing from the address following the HALT instruction When RESET pin is used to exit the device from the HALT mode and the two pin crystal resonator (CKI CKO) clock option is selected the contents of the Accumulator and the Timer T1 are undetermined following the reset All other information except the WATCHDOG Prescaler Counter contents is retained until continuing If the device comes out of the HALT mode through Brown Out reset the contents of data registers and RAM are unknown following the reset All information except the WATCHDOG Prescaler Counter contents is retained if the device exits the HALT mode through G7 pin or Multi-Input Wake-up G7 is the HALT-restart pin but it can still be used as an input If the device is not halted G7 can be used as a general purpose input If the Brown Out Enable mask option is selected the Brown Out circuit remains active during the HALT mode causing additional current to be drawn
Note To allow clock resynchronization it is necessary to program two NOP's immediately after the device comes out of the HALT mode The user must program two NOP's following the ``enter HALT mode'' (set G7 data bit) instruction
MICROWIRE PLUS
MICROWIRE PLUS is a serial synchronous bidirectional communications interface The MICROWIRE PLUS capability enables the device to interface with any of National Semiconductor's MICROWIRE peripherals (i e A D converters display drivers EEPROMS etc ) and with other microcontrollers which support the MICROWIRE PLUS interface It consists of an 8-bit serial shift register (SIO) with serial data input (SI) serial data output (SO) and serial shift clock (SK) Figure 4 shows the block diagram of the MICROWIRE PLUS interface The shift clock can be selected from either an internal source or an external source Operating the MICROWIRE PLUS interface with the internal clock source is called the Master mode of operation Operating the MICROWIRE PLUS interface with an external shift clock is called the Slave mode of operation
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MICROWIRE PLUS (Continued)
MICROWIRE PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE PLUS arrangement to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow k 8 bits to shift The device may enter the MICROWIRE PLUS mode either as a Master or as a Slave Figure 5 shows how two devices and several peripherals may be interconnected using the MICROWIRE PLUS arrangement MASTER MICROWIRE PLUS OPERATION In the MICROWIRE PLUS Master mode of operation the shift clock (SK) is generated internally by the device The MICROWIRE PLUS Master always initiates all data exchanges (See Figure 5 ) The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register Table IV summarizes the bit settings required for Master mode of operation SLAVE MICROWIRE PLUS OPERATION In the MICROWIRE PLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register Table IV summarizes the settings required to enter the Slave mode of operation The user must set the BUSY flag immediately upon entering the Slave mode This will ensure that all data bits sent by the Master will be shifted properly After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated (See Figure 5 )
TL DD 12851-16
FIGURE 4 MICROWIRE PLUS Block Diagram The CNTRL register is used to configure and control the MICROWIRE PLUS mode To use the MICROWIRE PLUS the MSEL bit in the CNTRL register is set to one The SK clock rate is selected by the two bits S0 and S1 in the CNTRL register Table III details the different clock rates that may be selected TABLE III S1 0 0 1 where tC is the instruction cycle time S0 0 1 x SK Cycle Time 2tC 4tC 8tC
TL DD 12851 - 17
FIGURE 5 MICROWIRE PLUS Application
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MICROWIRE PLUS (Continued)
TABLE IV G4 G5 Config Config Bit Bit 1 0 1 0 1 1 0 0 SO G4 Fun G5 Fun Intl SK G6 Fun SI SI SI SI Operation MICROWIRE Master MICROWIRE Master MICROWIRE Slave MICROWIRE Slave to decrement either on a positive edge or on a negative edge Upon underflow the contents of the register R1 are automatically copied into the counter The underflow can also be programmed to generate an interrupt (See Figure 6) MODE 3 TIMER WITH CAPTURE REGISTER Timer T1 can be used to precisely measure external frequencies or events in this mode of operation The timer T1 counts down at the instruction cycle rate Upon the occurrence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1 Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge In this mode the user can elect to be interrupted on the specified trigger edge (See Figure 7 )
TRI-STATE Int SK SO Ext SK
TRI-STATE Ext SK
TIMER COUNTER The device has a powerful 16-bit timer with an associated 16-bit register enabling it to perform extensive timer functions The timer T1 and its register R1 are each organized as two 8-bit read write registers Control bits in the register CNTRL allow the timer to be started and stopped under software control The timer-register pair can be operated in one of three possible modes Table V details various timer operating modes and their requisite control settings MODE 1 TIMER WITH AUTO-LOAD REGISTER In this mode of operation the timer T1 counts down at the instruction cycle rate Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down The timer underflow can be programmed to interrupt the microcontroller A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows This allows the generation of square-wave outputs or pulse width modulated outputs under software control (See Figure 6 )
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FIGURE 7 Timer Capture Mode Block Diagram TIMER PWM APPLICATION Figure 8 shows how a minimal component D A converter can be built out of the Timer-Register pair in the Auto-Reload mode The timer is place in the ``Timer with auto reload'' mode and the TIO pin is selected as timer output At the outset the TIO pin is set high the timer T1 holds the on time and the register R1 holds the signal off time Setting TRUN bit starts the timer which counts down at the instruction cycle rate The underflow toggles the TIO output and copies the off time into the timer which continues to run By alternately loading in the on time and the off time at each successive interrupt a PWM frequency can be easily generated
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FIGURE 6 Timer Counter Auto Reload Mode Block Diagram MODE 2 EXTERNAL COUNTER In this mode the timer T1 becomes a 16-bit external event counter The counter counts down upon an edge on the TIO pin Control bits in the register CNTRL program the counter FIGURE 8 Timer Application
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MICROWIRE PLUS (Continued)
TABLE V Timer Operating Modes CNTRL Bits 765 000 001 010 011 100 101 110 111 Operating Mode External Counter W Auto-Load Reg External Counter W Auto-Load Reg Not Allowed Not Allowed Timer W Auto-Load Reg Timer W Auto-Load Reg Toggle TIO Out Timer W Capture Register Timer W Capture Register T Interrupt Timer Underflow Timer Underflow Not Allowed Not Allowed Timer Underflow Timer Underflow TIO Pos Edge TIO Neg Edge Timer Counter On TIO Pos Edge TIO Pos Edge Not Allowed Not Allowed tC tC tC tC
WATCHDOG
The device has an on board 8-bit WATCHDOG timer The timer contains an 8-bit READ WRITE down counter clocked by an 8-bit prescaler Under software control the timer can be dedicated for the WATCHDOG or used as a general purpose counter Figure 9 shows the WATCHDOG timer block diagram MODE 1 WATCHDOG TIMER The WATCHDOG is designed to detect user programs getting stuck in infinite loops resulting in loss of program control or ``runaway'' programs The WATCHDOG can be enabled or disabled (only once) after the device is reset as a result of Brown Out reset or external reset On power-up the WATCHDOG is disabled The WATCHDOG is enabled by writing a 1 to WDREN bit (resides in WDREG register) Once enabled the user program should write periodically into the 8-bit counter before the counter underflows The 8-bit counter (WDCNT) is memory mapped at address 0CE Hex The counter is loaded with n-1 to get n counts The counter underflow resets the device but does not disable the WATCHDOG Loading the 8-bit counter initializes the prescaler with FF Hex and starts the prescaler counter Prescaler and counter are stopped upon counter underflow Prescaler and counter are each loaded with FF Hex when the device goes into the HALT mode The prescaler is used for crystal resonator start-up when the device exits the HALT mode through Multi-Input Wake-up In this case the prescaler counter contents are changed MODE 2 TIMER In this mode the prescaler counter is used as a timer by keeping the WDREN (WATCHDOG reset enable) bit at 0 The counter underflow sets the WDUDF (underflow) bit and the underflow does not reset the device Loading the 8-bit counter (load n-1 for n counts) sets the WDTEN bit (WATCHDOG Timer Enable) to ``1'' loads the prescaler with FF and starts the timer The counter underflow stops the timer The WDTEN bit serves as a start bit for the WATCHDOG timer This bit is set when the 8-bit counter is loaded by the user program The load could be as a result of WATCHDOG service (WATCHDOG timer dedicated for WATCHDOG function) or write to the counter (WATCHDOG timer used as a general purpose counter) The bit is cleared upon Brown Out reset WATCHDOG reset or external reset The bit is not memory mapped and is transparent to the user program Control Status Bits WDUDF WATCHDOG Timer Underflow Bit This bit resides in the CNTRL2 Register The bit is set when the WATCHDOG timer underflows The underflow resets the device if the WATCHDOG reset enable bit is set (WDREN e 1) Otherwise WDUDF can be used as the timer underflow flag The bit is cleared upon Brown-Out reset external reset load to the 8-bit counter or going into the HALT mode It is a read only bit WDREN WD Reset Enable WDREN bit resides in a separate register (bit 0 of WDREG) This bit enables the WATCHDOG timer to generate a reset The bit is cleared upon Brown Out reset or external reset The bit under software control can be written to only once (once written to the hardware does not allow the bit to be changed during program execution) WDREN e 1 WATCHDOG reset is enabled WDREN e 0 WATCHDOG reset is disabled Table VI shows the impact of Brown Out Reset WATCHDOG Reset and External Reset on the Control Status bits
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WATCHDOG (Continued)
TABLE VI WATCHDOG Control Status Parameter 8-bit Prescaler 8-bit WD counter WDREN bit WDUDF bit WDTEN Signal
Note 1 BOR is Brown Out Reset
HALT MODE FF FF Unchanged 0 Unchanged
WD Reset FF FF Unchanged Unchanged 0
EXT BOR (Note 1) Reset FF FF 0 0 0
Load Counter FF User Value No effect 0 1
TL DD 12851 - 21
FIGURE 9 WATCHDOG Timer Block Diagram
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Modulator Timer
The MODULATOR TIMER contains an 8-bit counter and an 8-bit autoreload register (MODRL address 0CF Hex) The Modulator Timer has two modes of operation selected by the control bit MC3 The Modulator Timer Control bits MC1 MC2 and MC3 reside in CNTRL2 Register MODE 1 MODULATOR The Modulator is used to generate high frequency pulses on the modulator output pin (L7) The L7 pin should be configured as an output The number of pulses is determined by the 8-bit down counter Under software control the modulator input clock can be either CKI or tC The tC clock is derived by dividing down the oscillator clock by a factor of 10 Three control bits (MC1 MC2 and MC3) are used for the Modulator Timer output control When MC2 e 1 and MC3 e 1 CKI is used as the modulator input clock When MC2 e 0 and MC3 e 1 tC is used as the modulator input clock The user loads the counter with the desired number of counts (256 max) and sets MC1 to start the counter The modulator autoreload register is loaded with n-1 to get n pulses CKI or tC pulses are routed to the modulator output (L7) until the counter underflows (Figure 10) Upon underflow the hardware resets MC1 and stops the counter The L7 pin goes low and stays low until the counter is restarted by the user program The user program has the responsibility to time-out the low time Unless the number of counts is changed the user program does not have to load the counter each time the counter is started The counter can simply be started by setting the MC1 bit Setting MC1 by software will load the counter with the value of the autoreload register The software can reset MC1 to stop the counter MODE 2 PWM TIMER The counter can also be used as a PWM Timer In this mode an 8-bit register is used to serve as an autoreload register (MODRL) a 50% Duty Cycle When MC1 is 1 and MC2 MC3 are 0 a 50% duty cycle free running signal is generated on the L7 output pin (Figure 11) The L7 pin must be configured as an output pin In this mode the 8-bit counter is clocked by tC Setting the MC1 control bit by software loads the counter with the value of the autoreload register and starts the counter The counter underflow toggles the (L7) output pin The 50% duty cycle signal will be continuously generated until MC1 is reset by the user program b Variable Duty Cycle When MC3 e 0 and MC2 e 1 a variable duty cycle PWM signal is generated on the L7 output pin The counter is clocked by tC In this mode the 16-bit timer T1 along with the 8-bit down counter are used to generate a variable duty cycle PWM signal The timer T1 underflow sets MC1 which starts the down counter and it also sets L7 high (L7 should be configured as an output) When the counter underflows the MC1 control bit is reset and the L7 output will go low until the next timer T1 underflow Therefore the width of the output pulse is controlled by the 8-bit counter and the pulse duration is controlled by the 16-bit timer T1 (Figure 12) Timer T1 must be configured in ``PWM Mode Toggle TIO Out'' (CNTRL1 Bits 7 6 5 e 101) Table VII shows the different operation modes for the Modulator Timer TABLE VII Modulator Timer Modes Control bits in CNTRL2(00CC) MC3 0 0 0 1 1 MC2 0 0 1 0 1 MC1 0 1 X X X Normal I O 50% duty cycle mode (clocked by tC) Variable duty cycle mode (clocked by tC) using Timer 1 underflow Modulator mode (clocked by tC) Modulator mode (clocked by CKI) OPERATION MODE L7 Function
Note MC1 MC2 and MC3 control bits are cleared upon reset
INTERNAL DATA BUS
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FIGURE 10 Mode 1 Modulator Block Diagram Output Waveform
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Modulator Timer (Continued)
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FIGURE 11 Mode 2a 50% Duty Cycle Output
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TL DD 12851 - 26
FIGURE 12 Mode 2b Variable Duty Cycle Output
Comparator
The device has one differential comparator Ports L0 - L2 are used for the comparator The output of the comparator is brought out to a pin Port L has the following assignments L0 Comparator output L1 Comparator negative input L2 Comparator positive input THE COMPARATOR STATUS CONTROL BITS These bits reside in the CNTRL2 Register (Address 0CC) CMPEN Enables comparator (``1'' e enable) CMPRD Reads comparator output internally (CMPEN e 1 CMPOE e X) CMPOE Enables comparator output to pin L0 (``1'' e enable) CMPEN bit must be set to enable this function If CMPEN e 0 L0 will be 0 The Comparator Select Control bits are cleared on RESET (the comparator is disabled) To save power the program should also disable the comparator before the device enters the HALT mode The user program must set up L0 L1 and L2 ports correctly for comparator Inputs Output L1 and L2 need to be configured as inputs and L0 as output Table VIII shows the DC and AC characteristics for the comparator
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Comparator (Continued)
TABLE VIII DC and AC Characteristics (Note 1) 4V s VCC s 6V b40 C s TA s a 85 C Parameters Input Offset Voltage Input Common Mode Voltage Range Voltage Gain DC Supply Current (when enabled) Response Time VCC e 6 0V 100 mV Overdrive 500 mV Overdrive 1000 mV Overdrive 60 80 135 100 125 215 Conditions 0 4V k VIN k VCC b1 5V 04 300k 250 140 165 300 Min Typ
g10
Max
g25
Units mV V VV mA ns
VCC b1 5
Note 1 For comparator output current characteristics see L-Port specs
Multi-Input Wake-Up
The Multi-Input Wake-Up feature is used to return (wake-up) the device from the HALT mode Figure 13 shows the MultiInput Wake-Up logic An example may serve to clarify this procedure Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L port bit 5 where bit 5 has previously been enabled for an input The program would be as follows RBIT 5 WKEN SBIT 5 WKEDG RBIT 5 WKPND SBIT 5 WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wake-Up a safety procedure should also be followed to avoid inherited pseudo wake-up conditions After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled the associated edge select bits in WKEDG should be set or reset for the desired edge selects followed by the associated WKPND bits being cleared This same procedure should be used following RESET since the L port inputs are left floating as a result of RESET The occurrence of the selected trigger condition for Multi-Input Wake-Up is latched into a pending register called Reg WKPND The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin The user has the responsibility of clearing these pending flags Since the Reg WKPND is a pending register for the occurrence of selected wake-up conditions the device will not enter the HALT mode if any wake-up bit is both enabled and pending Setting the G7 data bit under this condition will not allow the device to enter the HALT mode Consequently the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode If a crystal oscillator is being used the wake-up signal will not start the chip running immediately since crystal oscillators have a finite start up time The WATCHDOG timer prescaler generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions In this case upon detecting a valid wake-up signal only the oscillator circuitry and the WATCHDOG timer are enabled The WATCHDOG timer prescaler is loaded with a value of FF Hex (256 counts) and is clocked from the tC instruction cycle clock The tC clock is derived dividing down the oscillator clock by a factor of 10 A Schmitt trigger following the CKI on-chip inverter ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs 20
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FIGURE 13 Multi-Input Wake-Up Logic This feature utilizes the L Port The user selects which particular L port bit or combination of L Port bits will cause the device to exit the HALT mode Three 8-bit memory mapped registers Reg WKEN Reg WKEDG and Reg WKPND are used in conjunction with the L port to implement the MultiInput Wake-Up feature All three registers Reg WKEN Reg WKPND and Reg WKEDG are read write registers and are cleared at reset except WKPND WKPND is unknown on reset The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition) This selection is made via the Reg WKEDG which is an 8-bit control register with a bit assigned to each L Port pin Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin Resetting the bit selects the trigger condition to be a positive edge Changing an edge select entails several steps in order to avoid a pseudo wake-up condition as a result of the edge change First the associated WKEN bit should be reset followed by the edge select change in WKEDG Next the associated WKPND bit should be cleared followed by the associated WKEN bit being re-enabled
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Multi-Input Wake-Up (Continued)
This Schmitt trigger is not part of the oscillator closed loop The start-up time-out from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip
Any of the three instructions can be used to return from a hardware interrupt subroutine The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop
Note There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit If this occurs when a single cycle instruction is being used to reset the interrupt enable bit the interrupt enable bit will be reset but an interrupt may still occur This is because interrupt processing is started at the same time as the interrupt bit is being reset To avoid this scenario the user should always use a two three or four cycle instruction to reset interrupt enable bits
Interrupts
The device has a sophisticated interrupt structure to allow easy interface to the real world There are three possible interrupt sources as shown below A maskable interrupt on external GO input (positive or negative edge sensitive under software control) A maskable interrupt on timer carry or timer capture A non-maskable software error interrupt on opcode zero INTERRUPT CONTROL The GIE (global interrupt enable) bit enables the interrupt function This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources This bit is reset when interrupt is acknowledged ENI and ENTI bits select external and timer interrupts respectively Thus be user can select either or both source to interrupt the microcontroller when GIE is enabled IEDG selects the external interrupt edge (0 rising edge 1 e falling edge) The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt IPND and TPND bits signal which interrupt is pending After an interrupt is acknowledged the user can check these two bits to determine which interrupt is pending This permits the interrupts to be prioritized under software The pending flags have to be cleared by the user Setting the GIE bit high inside the interrupt subroutine allows nested interrupts The software interrupt does not reset the GIE bit This means that the controller can be interrupted by other interrupt sources while servicing the software interrupt INTERRUPT PROCESSING The interrupt once acknowledged pushes the program countermen counter (PC) onto the stack and the stack pointer (SP) is decremental twice The Global Interrupt Enable (GIE) bit is reset to disable further interrupts The microcontroller then vectors to the address 00FFH and resumes execution from that address This process takes 7 cycles to complete At end of the interrupt subroutine any of the following three instructions return the processor back to the main program RET RETSK or RETI Either one of the three instructions will pop the stack into the program counter (PC) The stack pointer is then incremented twice The RETI instruction additionally sets the GIE bit to re-enable further interrupts
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FIGURE 14 Interrupt Block Diagram DETECTION OF ILLEGAL CONDITIONS The device incorporates a hardware mechanism that allows it to detect illegal conditions which may occur from coding errors noise and ``brown out'' voltage drop situations Specifically it detects cases of executing out of undefined ROM area and unbalanced stack situations Reading an undefined ROM location returns 00 (hexadecimal) as its contents The opcode for a software interrupt is also ``00'' Thus a program accessing undefined ROM will cause a software interrupt Reading undefined RAM location returns an FF (hexadecimal) The subroutine stack on the device grows down for each subroutine call By initializing the stack pointer to the top of RAM the first unbalanced return instruction will cause the stack pointer to address undefined RAM As a result the program will attempt to execute from FFFF (hexadecimal) which is an undefined ROM location and will trigger a software interrupt
Control Registers
CNTRL1 REGISTER (ADDRESS 00EE) The Timer and MICROWIRE control register contains the following bits SL1 and SL0 Select the MICROWIRE clock divide-by (00 e 2 01 e 4 1x e 8) IEDG External interrupt edge polarity select MSEL Selects G5 and G4 as MICROWIRE signals SK and SO respectively TRUN Used to start and stop the timer counter (1 e run 0 e stop) TC1 Timer T1 Mode Control Bit TC2 Timer T1 Mode Control Bit TC3 Timer T1 Mode Control Bit
TC1 Bit 7 TC2 TC3 TRUN MSEL IEDG SL1 SL0 Bit 0
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Control Registers (Continued)
PSW REGISTER (ADDRESS 00EF) The PSW register contains the following select bits GIE ENI BUSY PND ENTI TPND C HC
HC Bit 7 C
Memory Map
All RAM ports and registers (except A and PC) are mapped into data memory address space TABLE X Memory Map ADDRESS 00 - 6F 70 - 7F 80 - BF C0 - C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 - DB DC DD - DF E0 - EF E0 - E7 E8 E9 EA EB EC ED EE EF F0 - FF FC FD FE CONTENTS On-Chip RAM bytes (112 bytes) Unused RAM address (Reads as all ones) Unused RAM address (Reads Undefined Data) Reserved MIWU Edge Select Register (Reg WKEDG) MIWU Enable Register (Reg WKEN) MIWU Pending Register (Reg WKPND) Reserved Control2 Register (CNTRL2) WATCHDOG Register (WDREG) WATCHDOG Counter (WDCNT) Modulator Reload (MODRL) Port L Data Register Port L Configuration Register Port L input Pins (read only) Reserved for Port L Port G Data Register Port G Configuration Register Port G Input pins (read only) Port I Input pins (read only) Reserved for Port C Port D Data Register Reserved for Port D On-Chip Functions and Registers Reserved for Future Parts Reserved MICROWIRE Shift Register Timer Lower Byte Timer Upper Byte Timer1 Autoreload Register Lower Byte Timer1 Autoreload Register Upper Byte CNTRL1 Control Register PSW Register On-Chip RAM mapped as Registers X Register SP Register B Register
Global interrupt enable (enables interrupts) External interrupt enable MICROWIRE busy shifting flag External interrupt pending Timer T1 interrupt enable Timer T1 interrupt pending (timer Underflow or capture edge) Carry Flip flop Half carry Flip flop
TPND ENTI IPND BUSY ENI GIE Bit 0
The Half-Carry bit is also effected by all the instructions that effect the Carry flag The flag values depend upon the instruction For example after executing the ADC instruction the values of the Carry and the Half-Carry flag depend upon the operands involved However instructions like SET C and RESET C will set and clear both the carry flags Table IX lists the instructions that effect the HC and the C flags TABLE IX Instructions Effecting HC and C Flags Instr ADC SUBC SET C HC Flag C Flag
Depends on operands Depends on operands Depends on operands Depends on operands Set Set Set
RESET C Set RRC
Depends on operands Depends on operands
CNTRL2 REGISTER (ADDRESS 00CC)
MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF RWRWRW Bit 7 RW RO RW RO Bit 0 unused
MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF
Modulator Timer Control Bit Modulator Timer Control Bit Modulator Timer Control Bit Comparator Enable Bit Comparator Read Bit Comparator Output Enable Bit WATCHDOG Timer Underflow Bit (Read Only)
WDREN REGISTER (ADDRESS 00CD) WDRENWATCHDOG Reset Enable Bit (Write Once Only)
UNUSED Bit 7 WDREN Bit 0
Reading other unused memory locations will return undefined data
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Addressing Modes
There are ten addressing modes six for operand addressing and four for transfer of control OPERAND ADDRESSING MODES REGISTER INDIRECT This is the ``normal'' addressing mode for the chip The operand is the data memory addressed by the B or X pointer REGISTER INDIRECT WITH AUTO POST INCREMENT OR DECREMENT This addressing mode is used with the LD and X instructions The operand is the data memory addressed by the B or X pointer This is a register indirect mode that automatically post increments or post decrements the B or X pointer after executing the instruction DIRECT The instruction contains an 8-bit address field that directly points to the data memory for the operand IMMEDIATE The instruction contains an 8-bit immediate field as the operand SHORT IMMEDIATE This addressing mode issued with the LD B instruction where the immediate is k 16 The instruction contains a 4-bit immediate field as the operand INDIRECT This addressing mode is used with the LAID instruction The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory TRANSFER OF CONTROL ADDRESSING MODES RELATIVE This mode is used for the JP instruction with the instruction field being added to the program counter to produce the next instruction address JP has a range from b31 to a 32 to allow a one byte relative jump (JP a 1 is implemented by a NOP instruction) There are no ``blocks'' or ``pages'' when using JP since all 15 bits of the PC are used ABSOLUTE This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC) This allows jumping to any location in the current 4k program memory segment ABSOLUTE LONG This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC) This allows jumping to any location in the entire 32k program memory space INDIRECT This mode is used with the JID instruction The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory The contents of this program memory location serves as a partial address (lower 8 bits of PC) for the jump to the next instruction
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Instruction Set
REGISTER AND SYMBOL DEFINITIONS Registers A 8-bit Accumulator register B 8-bit Address register X 8-bit Address register SP 8-bit Stack pointer register PC 15-bit Program counter register PU Upper 7 bits of PC PL Lower 8 bits of PC C 1-bit of PSW register for carry HC 1-bit of PSW register for half carry GIE 1-bit of PSW register for global interrupt enable Instr ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT X LD LD LD X X LD LD LD CLRA INC DEC LAID DCOR RRC SWAP SC RC IFC IFNC JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Addr Addr Disp Addr Addr A A A A A A A A MemI MemI MemI MemI MemI MemI MemI MemI Function Add Add with carry Subtract with carry Logical AND Logical OR Logical Exclusive-OR IF equal IF greater than IF B not equal Decrement Reg skip if zero Set bit Reset bit If bit Exchange A with memory Load A with memory Load Direct memory Immed Load Register memory Immed Exchange A with memory B Exchange A with memory X Load A with memory B Load A with memory X Load memory immediate Clear A Increment A Decrement A Load A indirect from ROM Decimal Correct A Rotate right through carry Swap nibbles of A Set C Reset C If C If Not C Jump absolute long Jump absolute Jump relative short Jump subroutine long Jump subroutine Jump indirect Return from subroutine Return and skip Return from interrupt Generate an interrupt No operation Symbols B Memory indirectly addressed by B register X Memory indirectly addressed by X register MD Direct addressed memory Mem Direct addressed memory or B MemI Direct addressed memory B or Immediate data Imm 8-bit Immediate data Reg Register memory addresses F0 to FF (Includes B X and SP) Bit Bit number (0 to 7) w Loaded with Exchanged with Register Operation A w A a MemI A w A a MemI a C C w Carry A w A a MemI a C C w Carry A w A and MemI A w A or MemI A w A xor MemI Compare A and MemI Do next if A e MemI Compare A and MemI Do next if A l MemI Do next if lower 4 bits of B not e Imm Reg w Reg b 1 skip if Reg goes to 0 1 to Mem bit (bit e 0 to 7 immediate) 0 to Mem bit (bit e 0 to 7 immediate) If Mem bit is true do next instruction A Mem A w MemI Mem w Imm Reg w Imm A B (B w Bg1) A X (X w Xg1) A w B (B w Bg1) A w X (X w Xg1) B w Imm (B w Bg1) Aw0 AwAa1 AwAb1 A w ROM(PU A) A w BCD correction (follows ADC SUBC) x A0 x C C x A7 x A3 A0 A7 A4 Cw1 Cw0 If C is true do next instruction If C is not true do next instruction PC w ii (ii e 15 bits 0 to 32k) PC11 PC0 w i (i e 12 bits) PC15 PC12 remain unchanged PC w PC a r (r is b31 to a 32 not 1) SP w PL SPb1 w PU SPb2 PC w ii SP w PL SPb1 w PU SPb2 PC11 PC0 w ii PL w ROM(PU A) SP a 2 PL w SP PU w SPb1 SP a 2 PL w SP PU w SPb1 Skip next instruction SP a 2 PL w SP PU w SPb1 GIE w 1 SP w PL SPb1 w PU SPb2 PC w 0FF PC w PC a 1
Reg Mem Mem Mem A Mem A MemI Mem Imm Reg Imm A Bg A Xg A Bg A Xg Bg Imm
A A A A A
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Opcode Table
Upper Nibble Bits 7-4 D i DRSZ 0F0 i DRSZ 0F1 i DRSZ 0F2 X A Ba X A Bb LAID JID XA X OR A NOP IFNC LD A B a LD A Bb JMPL JSRL LD A B LD B i LD A Md X A Md RETSK RET RETI LD Bb i DECA SBIT 3B SBIT 4B SBIT 5B SBIT 6B SBIT 7B LD B a i INCA SBIT 2B RBIT 2B RBIT 3B RBIT 4B RBIT 5B RBIT 6B RBIT 7B SBIT 1B RBIT 1B LD A i IFC SBIT 0B RBIT 0B LD B 7 LD B 6 LD B 5 LD B 4 LD B 3 LD B 2 LD B 1 LD B 0 i OR A B IFBIT 7B LD B 8 XA B XOR A i XOR A B IFBIT DCORA 6B LD B 9 IFBNE 6 IFBNE 7 IFBNE 8 IFBNE 9 IFBNE 0A IFBNE 0B IFBNE 0C IFBNE 0D IFBNE 0E IFBNE 0F AND A i AND A B IFBIT SWAPA LD B 0A 5B IFBNE 5 ADD A i ADD A B IFBIT 4B CLRA LD B 0B IFBNE 4 JSR 0400-04FF JSR 0500-05FF JSR 0600-06FF JSR 0700-07FF JSR 0800-08FF JSR 0900-09FF IFGT A i IFGT A B IFBIT 3B LD B 0C IFBNE 3 JSR 0300-03FF IFEQ A i DRSZ 0F3 i DRSZ 0F4 i DRSZ 0F5 i DRSZ 0F6 i DRSZ 0F7 i DRSZ 0F8 i DRSZ 0F9 i DRSZ 0FA LD A X a i DRSZ 0FB LD A Xb i DRSZ 0FC i DRSZ 0FD i DRSZ 0FE i DRSZ 0FF LD A X DIR LD Md i X A Xb X A Xa i IFEQ A B IFBIT AB LD B 0D IFBNE 2 JSR 0200-02FF SC SUBC A i SUBC A B IFBIT 1B LD B 0E IFBNE 1 JSR 0100-01FF RRCA RC ADC A i ADC A B IFBIT 0B LD B 0F IFBNE 0 JSR 0000-00FF JMP JP a 17 0000-00FF JMP JP a 18 0100-01FF C B A 9 8 7 6 5 4 3 2 1 0 INTR JP a 2 Lower Nibble Bits 3-0 0 1 2 JP a 4 JMP JP a 21 0400-04FF JMP JP a 22 0500-05FF JMP JP a 23 0600-06FF JMP JP a 24 0700-07FF JMP JP a 25 0800-08FF JP a 5 JP a 6 JP a 7 JP a 8 JP a 9 JMP JP a 26 JP a 10 0900-09FF JSR JMP JP a 27 JP a 11 0A00-0AFF 0A00-0AFF JSR JMP JP a 28 JP a 12 0B00-0BFF 0B00-0BFF JSR JMP JP a 29 JP a 13 0C00-0CFF 0C00-0CFF JSR JMP JP a 30 JP a 14 0D00-0DFF 0D00-0DFF JSR JMP JP a 31 JP a 15 0E00-0EFF 0E00-0EFF JSR JMP JP a 32 JP a 16 0F00-0FFF 0F00-0FFF 3 4 5 6 7 8 9 A B C D E F
F
E
JPb15 JPb31 LD 0F0
JPb14 JPb30 LD 0F1
JPb13 JPb29 LD 0F2
JMP JP a 19 UJP a 3 0200-02FF JMP JP a 20 0300-03FF
JPb12 JPb28 LD 0F3
JPb11 JPb27 LD 0F4
JPb10 JPb26 LD 0F5
JPb9
JPb25 LD 0F6
JPb8
JPb24 LD 0F7
25
iA
JPb7
JPb23 LD 0F8
JPb6
JPb22 LD 0F9
JPb5
JPb21 LD 0FA
JPb4
JPb20 LD 0FB
JPb3
JPb19 LD 0FC
JPb2
JPb18 LD 0FD
JPb1
JPb17 LD 0FE
JPb0
JPb16 LD 0FF
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i is the immediate data Md is a directly addressed memory location is an unused opcode Note The opcode 60 Hex is also the opcode for IFBIT
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions requiring two bytes)
Instuctions Using A and C (Bytes Cycles) Instr CLRA INCA DECA LAID DCOR RRCA SWAPA SC RC IFC IFNC Bytes Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1
Most single byte instructions take one cycle time to execute
Skipped instructions require x number of cycles to be
skipped where x equals the number of bytes in the skipped instruction opcode The following tables shows the number of bytes and cycles for each instruction in the format byte cycle Arithmetic and Logic Instructions (Bytes Cycles) Instr ADD ADC SUBC AND OR XOR IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direct 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 Immediate 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Transfer of Control Instructions (Bytes Cycles) Instr JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Bytes Cycles 3 2 1 3 2 1 1 1 1 1 1 4 3 3 5 5 3 5 5 5 7 1
13 34 34 34
11 11 11
Memory Transfer Instructions (Bytes Cycles) Register Indirect B X A (Note a) LD A (Note a) LD B Imm LD B Imm LD Mem Imm LD Reg Imm
Note b IF B k 16 Note c IF B l 15
Instr
Direct
Immed
Register Indirect Auto Incr and Decr B a Bb X a Xb
X 23 23 13 13 22 1 1 (Note b) 2 3 (Note c)
11 11
12 12 13 13 22
22
33 23
Note a Memory location addressed by B or X or directly
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Mask Option
The mask programmable options are listed below The options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a variety of oscillator configurations and the Brown Out feature The following option information is to be sent to National along with the EPROM Contact the sales office for more details OPTION 1 CKI INPUT
e 1 Crystal (CKI 10) G7 CKO for crystal
Development Support
SUMMARY
iceMASTERTM IM-COP8 400 Full feature in-circuit emulation for all COP8 products A full set of COP8 Basic and Feature Family device and package specific probes are available
COP8 Debug Module Moderate cost in-circuit emulation
and development programming unit
COP8
configuration
e 2 External (CKI 10) G7 available as input e 3 R C (CKI 10) G7 available as input
Evaluation and Programming Unit EPUCOP880C low cost In-circuit simulation and development programming unit development Assembler Linker Librarian and Utility Software Development Tool Kit
Assembler COP8-DEV-IBMA A DOS installable cross
OPTION 2 ``Brown Out'' e 1 Enable Brown Out Detection e 2 Disable Brown Out Detection OPTION 3 BONDING e 1 28-Pin DIP SO Package e 2 20-Pin DIP SO Package How to Order To order a complete development package select the section for the microcontroller to be developed and order the parts listed Contact the sales office for more details
C Compiler COP8C A DOS installable cross development Software Tool Kit
OTP EPROM Programmer Support Covering needs
from engineering prototype pilot production to full production environments
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Development Support (Continued)
IceMASTER (IM) IN-CIRCUIT EMULATION The iceMASTER IM-COP8 400 is a full feature PC based in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products National is a resale vendor for these products See Figure 15 for configuration The iceMASTER IM-COP8 400 with its device specific COP8 Probe provides a rich feature set for developing testing and maintaining product
Watch windows content updated automatically at each
execution break
Instruction by instruction memory register changes displayed on source window when in single step operation
Single base unit and debugger software reconfigurable to
support the entire COP8 family only the probe personality needs to change Debugger software is processor customized and reconfigured from a master model file
Processor specific symbolic display of registers and bit
level assignments configured from master model file
Real-time in-circuit emulation full 2 4VDC-5 5VDC operation range full DC-10 MHz clock Chip options are programmable or jumper selectable
Halt Idle mode notification On-line HELP customized to specific processor using
master model file
Direct connection to application board by package compatible socket or surface mount assembly
Includes a copy of COP8-DEV-IBMA assembler and linker SDK IM Order Information Base Unit IM-COP8 400-1 IM-COP8 400-2 iceMASTER Probe MHW-840CJ28DWPC MHW-840CJ20DWPC MHW-SOIC28 MHW-SOIC20 28 DIP 20 DIP 28 SOIC Adapter Kit 20 SOIC Adapter Kit iceMASTER Base Unit 110V Power Supply iceMASTER Base Unit 220V Power Supply
Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM On-chip RAM and I O blocks are used directly or recreated on the probe as necessary
Full 4k frame synchronous trace memory Address instruction and 8 unspecified circuit connectable trace lines Display can be HLL source (e g C source) assembly or mixed
A full 64k hardware configurable break trace on trace
off control and pass count increment events
Tool set integrated interactive symbolic debugger supports both assembler (COFF) and C Compiler ( COD) linked object formats
Real time performance profiling analysis selectable
bucket definition
TL DD 12851 - 29
FIGURE 15 COP8 iceMASTER Environment
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Development Support (Continued)
IceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module is a PC based combination in-circuit emulation tool and COP8 based OTP EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products National is a resale vendor for these products See Figure 16 for configuration The iceMASTER Debug Module is a moderate cost development tool It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families Summary of features is as follows
Instruction by instruction memory register changes displayed when in single step operation
Debugger software is processor customized and reconfigured from a master model file
Processor specific symbolic display of registers and bit
level assignments configured from master model file
Halt Idle mode notification Programming menu supports full product line of programmable OTP and EPROM COP8 products Program data is taken directly from the overlay RAM
Programming of 44 PLCC and 68 PLCC parts requires
external programming adapters
Real-time in-circuit emulation full operating voltage
range operation full DC-10 MHz clock
All processor I O pins can be cabled to an application
development board with package compatible cable to socket and surface mount assembly
Includes wall mount power supply On-board VPP generator from 5V input or connection to
external supply supported Requires VPP level adjustment per the family programming specification (correct level is provided on an on-screen pop-down display)
Full 32 kbytes of loadable programming space that overlays (replaces) the on-chip ROM or EPROM On-chip RAM and I O blocks are used directly or recreated as necessary
On-line HELP customized to specific processor using
master model file
Includes a copy of COP8-DEV-IBMA assembler and linker SDK DM Order Information Debug Module Unit COP8-DM 840CJ Cable Adapters DM-COP8 28D DM-COP8 28D-SO DM-COP8 20D DM-COP8 20D-SO 28 DIP cable 28 DIP to 28 SOIC adapter 20 DIP cable 20 DIP to 20 SOIC adapter
100 frames of synchronous trace memory The display
can be HLL source (C source) assembly or mixed The most recent history prior to a break is available in the trace memory
Configured break points uses INTR instruction which is
modestly intrusive
Software only supported features are selectable Tool set integrated interactive symbolic debugger supports both assembler (COFF) and C Compiler ( COD) SDK linked object formats
TL DD 12851 - 30
FIGURE 16 COP8-DM Environment
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Development Support (Continued)
COP8 ASSEMBLER LINKER SOFTWARE DEVELOPMENT TOOL KIT National Semiconductor offers a relocateable COP8 macro cross assembler linker librarian and utility software development tool kit Features are summarized as follows COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products Features are summarized as follows
Basic and Feature Family instruction set by ``device''
type
ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application
Integrated utilities to generate ROM code file outputs DUMPCOFF utility This product is integrated as a part of MetaLink tools as a development kit fully supported by the MetaLink debugger It may be ordered separately or it is bundled with the MetaLink products at no additional cost Order Information Assembler SDK COP8-DEV-IBMA Assembler SDK on installable 3 5 PC DOS Floppy Disk Drive format Periodic upgrades and most recent version is available on National's BBS and Internet

Nested macro capability Extensive set of assembler directives Supported on PC DOS platform Generates National standard COFF output files Integrated Linker and Librarian
BITS data type extension Register declaration
with direct bit level definitions
pragma
C language support for interrupt routines Expert system rule based code generation and optimization
Performs consistency checks against the architectural
definitions of the target COP8 device
Generates program memory code Supports linking of compiled object or COP8 assembled
object formats
Global optimization of linked code Symbolic debug load format fully source level supported
by the MetaLink debugger INDUSTRY WIDE OTP EPROM PROGRAMMING SUPPORT Programming support in addition to the MetaLink development tools is provided by a full range of independent approved vendors to meet the needs from the engineering laboratory to full production Approved List
Manufacturer BP Microsystems Data I O
North America (800) 225-2102 (713) 688-4600 Fax (713) 688-0920 (800) 426-1045 (206) 881-6444 Fax (206) 882-1043 (510) 623-8860 (800) 624-8949 (919) 430-7915 (800) 638-2423 (602) 926-0797 Fax (602) 693-0681 (408) 263-6667 (916) 924-8037 Fax (916) 924-8065
Europe
a 49-8152-4183 a 49-8856-932616 a 44-0734-440011
Asia
a 852-234-16611 a 852-2710-8121
Call North America
a 886-2-764-0215 Fax a 886-2-756-6403
HI-LO ICE Technology MetaLink
Call Asia
a 44-1226-767404 Fax 0-1226-370-434 a 49-80 9156 96-0 Fax a 49-80 9123 86 a 41-1-9450300
a 852-737-1800
Systems General Needhams
a 886-2-917-3005 Fax a 886-2-911-1283
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Development Support (Continued)
AVAILABLE LITERATURE For more information please see the COP8 Basic Family User's Manual Literature Number 620895 COP8 Feature Family User's Manual Literature Number 620897 and National's Family of 8-bit Microcontrollers COP8 Selection Guide Literature Number 630009 DIAL-A-HELPER SERVICE Dial-A-Helper is a service provided by the Microcontroller Applications group The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board System (BBS) via data modem as an FTP site on the Internet via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Netscape or Mosaic The Dial-A-Helper system provides access to an automated information storage and retrieval system The system capabilities include a MESSAGE SECTION (electronic mail when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found DIAL-A-HELPER BBS via a Standard Modem Modem CANADA U S (800) NSC-MICRO (800) 672-6427 EUROPE ( a 49) 0-8141-351332 Baud Set-up 14 4k Length Parity Stop Bit 24 Hrs 8-Bit None 1 7 Days DIAL-A-HELPER via a WorldWide Web Browser ftp nscmicro nsc com National Semiconductor on the WorldWide Web See us on the WorldWide Web at http www national com CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National's customer response centers CANADA U S Tel email EUROPE email Deutsch Tel English Tel Fran ais Tel Italiano Tel JAPAN S E ASIA Tel Beijing Tel Shanghai Tel (800) 272-9959 support tevm2 nsc com
europe support nsc com
a 49 (0) 180-530 85 85 a 49 (0) 180-532 78 32 a 49 (0) 180-532 93 58 a 49 (0) 180-534 16 80 a 81-043-299-2309
( a 86) 10-6856-8601 ( a 86) 21-6415-4092
Hong Kong Tel ( a 852) 2737-1600 Korea Tel Malaysia Tel Singapore Tel Taiwan Tel AUSTRALIA INDIA Tel Tel ( a 82) 2-3771-6909 ( a 60-4) 644-9061 ( a 65) 255-2226
a 886-2-521-3288
Operation
( a 61) 3-9558-9999 ( a 91) 80-559-9467
DIAL-A-HELPER via FTP ftp nscmicro nsc com user anonymous password username yourhost site domain
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number COP842CJ-XXX M or COP942CJ-XXX M NS Package Number M20B
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number COP840CJ-XXX M or COP940CJ-XXX M NS Package Number M28B
Order Number COP842CJ-XXX N or COP942CJ-XXX N NS Package Number N20A
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COP840CJ COP842CJ COP940CJ COP942CJ 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number COP840CJ-XXX N or COP940CJ-XXX N NS Package Number N28B
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018
2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness
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National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80
National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960
National Semiconductor Japan Ltd Tel 81-043-299-2308 Fax 81-043-299-2408
National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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